HierarchyFilesModulesSignalsTasksFunctionsHelp
/*
  Copyright (c) 2004 Pablo Bleyer Kocik.

  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice,
  this list of conditions and the following disclaimer in the documentation
  and/or other materials provided with the distribution.

  3. The name of the author may not be used to endorse or promote products
  derived from this software without specific prior written permission.

  THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED
  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
  EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  POSSIBILITY OF SUCH DAMAGE.
*/

/*
  kcpsmx test
*/

`define test_file "../test/test3.rmh"

`include "timescale_inc.v"
`include "kcpsmx_inc.v"

module kcpsmx_tbIndex;

parameter tck = 10, program_size = 1024;

reg clk, rst, ir; // clock, reset, interrupt req
wire [`code_depth-1:0] ad; // instruction address
reg [`operand_width-1:0] prt[0:`port_size-1];
wire [`operand_width-1:0] pa, po; // port id, port out
wire rd, wr; // read strobe, write strobe
`ifdef HAS_INTERRUPT_ACK
wire ia; // interrupt ack
`endif

wire [`code_width-1:0] di;
wire [`operand_width-1:0] pi = prt[pa]; // port in

blockram #(.width(`code_width),.depth(`code_depth)) rom(
  .clk(clk),
  .rst(rst),
  .en(1),
  .we(0),
  .ad(ad),
  .di(0),
  .do(di)
);

kcpsmx dut(
  .clk(clk),
  .reset(rst),
  .address(ad),
  .instruction(di),
  .port_id(pa),
  .read_strobe(rd),
  .write_strobe(wr),
  .in_port(pi),
  .out_port(po),
  .interrupt(ir)
`ifdef HAS_INTERRUPT_ACK
  , .interrupt_ack(ia)
`endif
);

always #(tck/2) clk = ~clk;

always @(posedge clk) if (wr) prt[pa] <= po;

initial begin
  $dumpvars(1, dut);
  $dumpfile("kcpsmx_tb.vcd");
  $readmemh(`test_file, rom.ram);
end

integer i;
initial begin
  for (i=0; i<`port_size; i=i+1) prt[i] = i; // init ports
  clk = 0; rst = 1; ir = 0;
  #20;
  @(negedge clk) rst = 0; // free processor

  #300;
  @(negedge clk) ir = 1;
  @(negedge clk) ;
  @(negedge clk) ir = 0;

  #(program_size*tck+100) $finish;
end

endmodule


[Up: kcpsmx_tb rom]
module blockramIndex(
  clk, rst,
  en, we, ad, di, do
);
parameter width = 8, depth = 10;

input clk, rst, en, we;
input [depth-1:0] ad;
input [width-1:0] di;
output reg [width-1:0] do;

reg [width-1:0] ram[0:(1<<depth)-1];

always @(posedge clk)
  if (rst) do <= 'hx;
  else if (en)
    if (we) ram[ad] <= di;
    else do <= ram[ad];

endmodule

HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Maintained by: pbleyer2004N@SPAMembedded.cl
Created:Sun Oct 24 04:56:28 2004
From: kcpsmx_tb.v

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help